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description the CXA2542AR is a bipolar ic developed for cd player rf signal processing and servo control. features automatic focus bias adjustment circuit automatic tracking balance and gain adjustment circuits rf level control circuit interruption countermeasure circuit anti-shock circuit defect detection and prevention circuits rf i-v amplifier, rf amplifier apc circuit focus and tracking error amplifier focus, tracking and sled servo control circuits focus ok circuit mirror detection circuit single power supply and dual power supplies applications cd players structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1400 mw recommended operating conditions operating supply voltage v cc ?v ee 3.0 to 3.6 v 4.5 to 5.5 v ?1 CXA2542AR e98743b25 rf signal processing servo amplifier for cd player sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin lqfp (plastic)
?2 CXA2542AR block diagram ps1-4 tm1-7 tg1-2 fs1-4 ifb1-6 bal1-4 tog1-4 dfcto fe amp fo. bias window comp. tgfl trk. gain window comp. f iv amp e iv amp v ee v cc tg1 tm1 dfct tracking phase compensation iil data register input shift register address decoder sens selector output decoder v ee v ee e-f balance window comp. e f fei fdfct flb fe_o fe_m ta_m tg2 tgu srch fgd fset ld rftc rf_m rf_o rf_i cb cc1 fok cc2 cp pd1 pd sl_p sl_o iset v cc clk data xrst sl_m c. out xlt sens1 pd2 iv amp pd1 iv amp v cc v ee apc v ee laser power control rf summing amp v cc v ee level s fzc tzc atsc ball balh tgl tgh fol foh ldon lpcl lpc tgfl v ee v cc mirr dfct2 v ee v cc iset v cc v ee v cc tm5 tm6 v ee v cc tm3 tm4 fset tg2 focus phase compensation tm7 v ee v cc fs1 fs2 dfct fs4 iil ttl 42 44 45 46 48 2 3 4 6 7 8 9 10 11 12 1 13 27 28 29 30 39 38 36 35 34 31 32 33 14 15 16 17 18 19 20 21 22 23 24 25 26 tm2 v cc fzc comp. tzc comp. atsc window comp. mirr fok bal1 bal2 bal3 bal4 ifb1 v ee v cc ifb6 ifb5 ifb4 ifb3 ifb2 tog1 tog2 tog3 tog4 37 5 ta_o sens2 atsc lpfi teo vc tdfct tzc feo fzc pd2 47 40 41 43 iil ttl ttl iil v cc v ee v cc v ee v cc v ee cc1 xdfct1 int
3 CXA2542AR pin description pin no. symbol i/o equivalent circuit description 1 fei i 2 fdfct i focus error input. connects the capacitor for defect time constant. 3 fgd i ground this pin through a capacitor for cutting the focus servo high- frequency gain. 4 flb i external time constant setting pin for boosting the focus servo low- frequency. 5 fe_o o 12 ta_o o 15 sl_o o focus drive output. tracking drive output. sled drive output. 6 fe_m i focus amplifier inverted input. 147 50k 90k 2 6 250 5 12 15 147 100k 147 2 3 1 147 130k 68k 4 40k 470k 330k 3 4 7 srch i external time constant setting pin for generating the focus search waveform. 147 50k 11 20k 7
4 CXA2542AR 8 tgu i external time constant setting pin for switching the tracking high-frequency gain. 9 tg2 i external time constant setting pin for switching the tracking high-frequency gain. 10 fset i peak frequency setting pin for focus and tracking phase compensation amplifier. 11 ta_m i tracking amplifier inverted input. 13 sl_p i 14 sl_m i sled amplifier non-inverted input. sled amplifier inverted input. 147 2 13 147 100k 11 11 147k 15k 15k 10 20k 110k 82k 147 8 423k 470k 9 16 iset i connect the external resistor to set the current which determines the focus search, track jump, and sled kick levels. 147 50 16 147 22 14 pin no. symbol i/o equivalent circuit description
5 CXA2542AR 18 clk i 20 data i 17 v cc i positive power supply. serial data input from cpu. (no pull-up resistance) serial data transfer clock input from cpu. (no pull-up resistance) 19 xlt i 21 xrst i latch input from cpu. (no pull-up resistance) reset input; resets at low. (no pull-up resistance) 147 20 1k 18 20 147 20 4k 2.5p 19 21 22 c. out o 23 sens1 o 24 sens2 o track number count signal output. outputs fzc, dfct1, tzc, balh, tgh, foh, atsc, and others according to the command from cpu. outputs dfct2, mirr, ball, tgl, fol, and others according to the command from the cpu. 100k 147 20k 22 23 24 v cc 17 25 fok o focus ok comparator output. 147 20k 100k 40k 25 pin no. symbol i/o equivalent circuit description
6 CXA2542AR 26 cc2 i 28 cb i input for the rf summing amplifier output with capacitance coupled. connects the defect bottom hold capacitor. 147 43k 39k 26 75k 147 28 7.6k 240k 29 cp i connects the mirr hold capacitor. mirr comparator non-inverted input. 30 rf_i i 31 rf_o o 32 rf_m i 27 cc1 o 1.5k 100k 29 147 147 147 10k 10k 30 31 32 147 27 input for the rf summing amplifier output with capacitance coupled. rf summing amplifier output. eye- pattern check point. rf summing amplifier inverted input. the rf amplifier gain is determined by the resistance connected between this pin and rfo pin. rf summing amplifier output. used for the defect capacitance coupling. 33 rftc i external time constant setting pin during rf level control. 147 50 10 50 33 pin no. symbol i/o equivalent circuit description
7 CXA2542AR 34 ld o apc amplifier output. 35 pd i apc amplifier input. 36 37 pd1 pd2 i i rf i-v amplifier inverted input. connect these pins to the photo diode a + c and b + d pins. 147 10k 8.65k 100 2k 8k 36 37 0.2p 147 8 20 55k 10k 35 1k 10k 34 38 39 f e i i f i-v and e i-v amplifier inverted input. connect these pins to photo diodes f and e pins. 147 260k 12p 500 10 38 39 v ee 40 40 v ee negative power supply. pin no. symbol i/o equivalent circuit description
8 CXA2542AR 43 atsc i 44 tzc i window comparator input for atsc detection. tracking zero-cross comparator input. 41 teo o tracking error amplifier output. e-f signal is output. 45 tdfct i connects the capacitor for defect time constant. 147 75k 10 44 147 1k 100k 100k 1k 10 10 43 42 lpfi i comparator input for balance adjustment. (input from teo through lpf) 147 7 42 147 32k 15k 3k 15k 20k 150k 150k 6.6k 147 100k 3 41 45 pin no. symbol i/o equivalent circuit description
9 CXA2542AR 46 vc o (v cc + v ee )/2 dc voltage output. vc 50 120 120 46 15k 47 fzc i focus zero-cross comparator input. 147 7 300k 6k 54k 47 48 feo o focus error amplifier output. connected internally to the window comparator input for bias adjustment. 147 25p 174k 10 10 300 48 pin no. symbol i/o equivalent circuit description
10 CXA2542AR test t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 current consumption 1 current consumption 2 center amplifier output offset offset voltage gain max. output amplitude - high max. output amplitude - low offset voltage gain 1 voltage gain 2 voltage gain difference max. output voltage high max. output voltage low bias0 bias1 bias2 bias3 bias4 bias5 bias6 19 (off) 19 (off) 19 (off) 10, 13 10, 13 10, 13 10 13 13 10 rst rst rst rst rst rst rst 39f 39f 39f 39f 39f 39f 3bf 3be 3bd 3bb 3b7 3af 39f 17 40 36 37 36 37 36 37 36 37 37 36 17 40 46 31 31 31 31 48 48 48 48 48 48 48 48 48 48 48 48 1khz i/o ratio v2 = 0.2vdc v2 = 0.2vdc 1fb6: on 1khz i/o ratio 1khz i/o ratio v2 = 100mvdc v2 = 100mvdc ifb1, 2, 3, 4, 5, 6: off ifb1: on, bias0: reference ifb2: on, bias0: reference output gain difference with t15 ifb3: on, bias0: reference output gain difference with v17 ifb4: on, bias0: reference output gain difference with v18 ifb5: on, bias0: reference output gain difference with v19 ifb6: on, bias0: reference output gain difference with v20 12.0 25.0 100 70 16.5 1.2 120 15.6 15.6 3 1 560 29.0 5 5 5 5 5 18.5 18.5 0 13 19.5 1.4 1.3 0 18.6 18.6 0 1.4 1.3 718 22.7 6 6 6 6 6 25.0 12.0 100 70 22.5 1.0 120 21.6 21.6 3 1 1042 16.5 7 7 7 7 7 ma ma mv mv db v v mv db db db v v mv mv db db db db db item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit electrical characteristics (v cc = 1.5v, v ee = 1.5v, topr = 25 c) rf amplifier fe amplifier measure- ment pin
11 CXA2542AR foh threshold value fol threshold value offset gain up (f) gain up (e) voltage gain f0 voltage gain f1 voltage gain f2 voltage gain f3 voltage gain f4 voltage gain e0 voltage gain e1 voltage gain e2 voltage gain e3 voltage gain e4 max. output voltage high max. output voltage low output voltage 1 output voltage 2 output voltage 3 output voltage 4 ld off t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 14 15 14 14 14 14 14 15 15 15 15 15 1 1 9 38 39 38 39 38 38 38 38 38 39 39 39 39 39 38 39 35 35 35 35 35 39f 39f 34f 308 36f 308 36f 308 34f 34e 30f 34d 34b 347 34f 30f 00 30e 30d 30b 307 34f 308 34f 308 3c4 3c4 3c4 3c4 3c0 48 48 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 34 34 34 34 34 i fb6: on pin 1 voltage when sens1 (pin 23) goes from high to low ifb6: on pin 1 voltage when sens2 (pin 24) goes from high to low tog: off, bal1, 2, 3: on v1 = 2 khz, i/o ratio tog: off, bal1, 2, 3: on v1 = 2 khz, i/o ratio tog: off, bal1, 2, 3: on v1 = 2khz, tog: off i/o ratio v1 = 2khz, tog1: on reference to f0 v1 = 2khz, tog2: on reference to f0 v1 = 2khz, tog3: on reference to f0 v1 = 2khz, tog4: on reference to f0 v1 = 2khz, bal: off i/o ratio v1 = 2khz, bal1: on reference to e0 v1 = 2khz, bal2: on reference to e0 v1 = 2khz, bal3: on reference to e0 v1 = 2khz, bal4: on reference to e0 v1 = 1vdc, tog: off, bal1, 2, 3: on v1 = 1vdc, tog: off, bal1, 2, 3: on i1 = 364a i1 = 439a i1 = 515a 0.8ma sink i1 = 515a, ld: off 5 35 25 7.2 7.2 1.2 2.3 3.9 6.9 11.1 1.6 0.16 0.58 1.43 2.96 0.5 900 693 163 200 1.1 20 20 0 10.2 10.2 4.2 1.8 3.4 6.4 10.6 1.4 0.46 0.88 1.73 3.26 0.7 0.8 704 293 613 132 1.3 35 5 25 13.2 13.2 7.2 1.3 2.9 5.9 10.1 4.4 0.76 1.18 2.03 3.56 0.5 500 107 1063 500 mv mv mv db db db db db db db db db db db db v v mv mv mv mv v fe amplifier te amplifier apc test item sw conditions (on switches) sd input pin measure- ment pin measurement conditions min. typ. max. unit
12 CXA2542AR t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 50% limit 30% limit 50% limit 30% limit dc voltage gain fcs total gain feed through 1 fzc threshold value max. output voltage high max. output voltage low search voltage ( ) search voltage (+) dc voltage gain trk total gain feed through 1 max. output voltage high max. output voltage low jump output voltage ( ) jump output voltage (+) atsc threshold value ( ) atsc threshold value (+) tzc threshold value 8 8 10, 13 10, 13 1 1 20 1 1 5, 17 5, 17 18 3c7 3c5 3c7 3c5 08 00 08 00 08 08 02 03 25 20 25 20 25 20 25 2c 28 10 10 20 35 30 35 30 35 36 37 35 36 37 1 1 47 1 1 38 38 38 38 43 43 44 34 34 34 34 5 5 47 5 5 5 5 12 12 12 12 12 12 43 43 44 i1 = 273a output difference with lpc on/off i1 = 333a output difference with lpc on/off i1 = 742a output difference with lpc on/off i1 = 667a output difference with lpc on/off t9 + t47 i/o gain difference between sd = 00 and sd = 08 pin 47 voltage when sens1 (pin 23) goes from low to high v1 = 200mvdc v1 = 200mvdc dc gain between teo and ta_o t26 + t55 i/o gain difference between sd = 20 and sd = 25. v1 = 0.3vdc v1 = 0.3vdc input voltage when tg2 (pin 9) goes from vcc/2 to vcc input voltage when tg2 (pin 9) goes from vcc/2 to vcc pin 44 voltage when sens1 (pin 23) is 0v 725 315 1421 1215 17.4 37.5 123 1 721 399 11.4 16.8 1 652 437 25 7 20 1330 915 816 615 20.9 39.5 150 1.3 1.3 581 539 14.6 18.8 1.3 1.3 512 577 15 15 0 1935 1515 211 15 24.4 41.5 30 177 1 441 679 17.8 20.8 39 1 372 717 7 25 20 mv mv mv mv db db db mv v v mv mv db db db v v mv mv mv mv mv rf level controll focus servo tracking servo test item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit measure- ment pin
13 CXA2542AR t65 t66 t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 t77 t78 t79 t80 t81 t82 bal comp threshold value high bal comp threshold value low gain comp threshold value high gain comp threshold value low fok threshold value voltage gain feed through max. output voltage high max. output voltage low kick voltage 1 kick voltage 2 max. operating frequency 1 min. input operating voltage 1 max. input operating voltage 1 min. operating frequency 1 max. operating frequency 1 min. input operating voltage 1 max. input operating voltage 1 16 16 14 14 8 6, 7 6 6 6 8 8 8 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13 300 300 308 34f 308 34f 25 20 25 25 25 20 20 20 20 20 10 10 10 10 42 42 38 38 30 13 13 13 13 30 30 30 36 37 36 37 36 37 36 37 42 42 41 41 25 15 15 15 15 15 15 24 24 24 23 23 23 23 pin 42 voltage when sens1 (pin 23) goes from high to low pin 42 voltage when sens2 (pin 24) goes from high to low pin 41 voltage when sens1 (pin 23) goes from high to low pin 41 voltage when sens2 (pin 24) goes from low to high pin 30 voltage when pin 25 is 0v v1 = 100hz, i/o ratio i/o gain difference between sd = 20 and sd = 25. v1 = 400mvdc v1 = 400mvdc rev 1 fwd 1 measures at sens2 pin. measures at sens2 pin. measures at sens2 pin. measures at sens1 pin. measures at sens1 pin. measures at sens1 pin. measures at sens1 pin. 5 35 168 127 560 50 1 750 450 30 1.8 2.5 1.6 20 20 193 145 510 1.3 1.3 600 600 35 5 218 163 450 34 1 450 750 0.3 1 0.5 mv mv mv mv mv db db v v mv mv khz vp-p vp-p khz khz vp-p vp-p tracking servo fok sled servo mirror defect test item sw conditions (on switches) sd input pin measurement conditions min. typ. max. unit measure- ment pin
14 CXA2542AR gnd r19 10k c4 0.1 s3 s2 r9 47k c3 1000p s1 c1 1000p s19 s16 v2 ac dc i2 0.8ma c5 1 r13 30k s8 c7 0.01 c9 0.068 s7 r25 13k s6 c11 47 r23 60k r3 10k v1 ac dc gnd c2 33 gnd s17 gnd s18 gnd gnd gnd s20 gnd gnd v ee gnd r1 390k s15 r2 390k s14 gnd gnd gnd gnd r11 13k gnd r12 100k s5 r15 10k v cc r16 510k v cc c8 0.01 r18 13k gnd r17 100k gnd r24 5.1k gnd gnd v ee r26 120k v cc gnd clk c10 33 xlt data xrst v cc r20 10k v cc r21 10k v cc r22 10k v cc gnd c6 0.01 gnd gnd r14 10k r10 1m v ee v cc r8 330 v ee v cc i1 0a gnd f e v ee teo lpfi atsc tzc tdfct vc sens1 c. out xrst data xlt clk vcc iset sl_o sl_m sl_p sens2 fzc 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 41 42 45 46 47 40 44 43 fdfct fgd flb fe_o fe_m srch tgu tg2 fset ta_m ta_o fei pd1 pd ld rf_m rf_o rf_i cp cb cc1 fok rftc cc2 pd2 feo 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 48 r5 240k r6 240k s11 s12 r4 34k r7 34k s13 aa aa aa aa aa s10 s9 r26 100k electrical characteristics measurement circuit
15 CXA2542AR application circuit 1 (2.5v power supply) pd1 pd ld rf_m rf_o rf_i cp cb cc1 fok rftc cc2 vcc micro computer dsp 15k 22 3.3 driver 100k 0.015 60k v ee v ee 100k 150k 0.047 0.1 f e v ee teo lpfi atsc tzc tdfct vc 82k f e 8.2k sens1 c. out xrst data xlt clk vcc iset sl_o sl_m sl_p sens2 47k 330k 470p 0.022 0.022 fzc 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 41 42 45 46 47 40 44 43 0.01 0.01 0.1 680k 510k 0.015 2200p 0.1 0.1 100k 4.7 driver 0.033 vcc 100k driver 10k 10k 0.068 0.01 0.033 0.01 30k vcc 22 100 1 10h 100 500 v ee vcc 1k 3.3 a c b d pd ld 1m 1 v ee v ee fdfct fgd flb fe_o fe_m srch tgu tg2 fset ta_m ta_o fei pd2 feo 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 48 application circuit 2 (single +5v power supply) vcc micro computer dsp 15k 22 3.3 driver 100k 0.015 60k 100k 150k 0.047 0.1 f e v ee teo lpfi atsc tzc tdfct vc 82k f e 8.2k sens1 c. out xrst data xlt clk vcc iset sl_o sl_m sl_p sens2 47k 330k 470p 0.022 0.022 fzc 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 41 42 45 46 47 40 44 43 0.01 0.01 0.1 680k 510k 0.015 2200p 0.1 0.1 100k 4.7 driver 0.033 vcc 100k driver 10k 10k 0.068 0.01 0.033 0.01 30k vcc 22 100 1 10h 100 500 vcc 1k 3.3 a c b d pd ld 1m 1 fdfct fgd flb fe_o fe_m srch tgu tg2 fset ta_m ta_o fei pd1 pd ld rf_m rf_o rf_i cp cb cc1 fok rftc cc2 pd2 feo 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 48 vcc 10 10 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
16 CXA2542AR description of functions rf amplifier the photodiode currents input to the input pins (pd1 and pd2) are each i-v converted through a 58k ? equivalent resistor by the pd i-v amplifiers. these signals are added by the rf summing amplifier, and the photodiode (a + b + c + d) current-voltage converted voltage is output to the rfo pin. an eye-pattern check can be performed at this pin. the low frequency component of the rfo output voltage is 30k v rfo = 10k (va + vb 2v3) + v3 = 3 { 58k ? (ipd1 + ipd2) + v1 + v2 2v3} + v3, and the setting is v1 = v2 = v3, then v rfo = 174k ? (ipd1 + ipd2) + v3 1k 3.3 a c b d pd1 ipd1 pd2 ipd2 58k va 10k vc pd1 iv amp 58k vb 10k vc pd2 iv amp rf_m rf_o 30k rf summing amp 32 31 36 37 v1 v2 fok defect v3
17 CXA2542AR focus error amplifier feo fei fe_o fe_m pd2 pd1 sens1 sens2 r8 100k v ee 20mv focus phase compensation sens selector vh vin > vh l vin < vh h foh 20mv vl vin > vl h vin < vl l fol vc vc vc r11 100k driver gnd gnd c1 2200p r9 10k r10 10k r1 16k vc vc r4 32k r2 58k v cc r7 174k vc r5 32k r3 58k pd2 iv amp pd1 iv amp ifb6 32 ifb5 16 ifb4 8 ifb3 4 ifb2 2 ifb1 1 reset : ifb1 to ifb6 on 25mv/step b + d a + c vin r6 174k va vb fe amp 48 1 6 5 23 24 32 37 36 v2 rf v1 rf the focus error amplifier calculates the difference between outputs va and vb of the rf i-v amplifier, and outputs current-voltage converted voltage of the photodiode (a + c b d). the feo output voltage: 174k ? v feo = 32k ? (va vb) 174k ? = 32k ? {( 58k ? ipd1) ( 58k ? ipd2)} = 315.4k ? (ipd2 ipd1) the focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. the focus bias adjustment is performed by turning the focus bias adjustment switches (ifb1 to ifb6) on and off. the 6-bit focus bias adjustment switches are controlled with commands. ifb1 to ifb6 are all on after a reset. the voltage is varied by approximately 25mv per step.
18 CXA2542AR focus error amplifier offset adjustment (when adjusting the ic offset) the offset adjustment is performed by comparing the feo when the focus servo is off with the reference level. the feo and reference level are compared by the window comparator, and the comparison results are output from sens1 and sens2. (address d11 001110 d6 ) adjust the offset so that sens1 and sens2 are both high. set the reference level to the center 20mv. 25mv < 40mv < 50mv reference level width variable voltage per step variable voltage per 2 steps focus bias fine adjustment fine adjustment is performed by turning the focus bias adjustment switches (ifb1 to ifb6) on and off while monitoring a dsp jitter meter with the microcomputer. the 6-bit focus bias adjustment switches are controlled with commands.
19 CXA2542AR the difference between e i-v amplifier output ve and f i-v amplifier output vf is taken and output from teo. the tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. the balance adjustment is performed by varying the combined resistance value of the t-configured feedback resistance at the e i-v amplifier. e i-v amp feedback resistance = r1 + r4 + f i-v amp feedback resistance = r2 + r5 + = 403k ? vary the combined resistance value of the e i-v amplifier's feedback resistance by using the balance adjustment switches (bal1 to bal4). the gain adjustment is performed by resistance dividing the te amp output by the gain adjustment switches (tog1 to tog4). the balance and gain adjustment switches are controlled with commands. set the cut-off frequency of the external lpf between 10hz and 100hz. tracking error amplifier lpfi teo f clk data xrst xlt sens1 sens2 vin > vh l vin < vh h balh vh 20mv vc vin 20mv vc vl vin > vl h vin < vl l ball vin > vh l vin < vh h tgh vh 200mv vc vin 150mv vc vl vin > vl h vin < vl l tgl sens selector comand control cpu r23 100k r24 150k c3 0.01 c4 0.01 gnd gnd vc r21 6.6k r20 15k r19 32k r17 20k r22 3k r18 15k r16 96k te amp normal r14 13k r9 17k gain up gain up r8 17k vc r12 96k r13 13k v normal tgfl tgfl c2 12p r2 260k r5 13k r3 26k vc vc c1 12p r1 260k r4 6.8k vc e vf ve f i-v amp e i-v amp r7 110k r10 56k r11 27k r15 13k r6 75k re vc + 23 41 42 comand control bal1 bal2 bal3 bal4 tog4 tog3 tog2 tog1 38 39 24 21 20 19 18 r1 r4 re r2 r5 r3
20 CXA2542AR balance adjustment the balance adjustment is performed by passing the tracking error signal (teo signal) through the external lpf, extracting the offset dc, and comparing it to the reference level. however, the teo signal frequency distribution ranges form dc to 2khz. merely sending the signal through the lpf leaves lower frequency components, and the complete offset dc can not be extracted. to extract it, monitor the teo signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the lpf. use the c.out output to check this frequency. the offset dc and reference level are compared by the window comparator. the comparison signal is output from the sens1 and sens2 pins. (address d11 001100 d6 ) adjust the balance so that the sens1 and sens2 pins are both high. gain adjustment gain adjustment is performed by passing the teo signal through the hpf and comparing the ac component to the reference level. the ac component is generated by taking the difference between te and the offset dc input to pin 42. the ac component and reference level are compared by the window comparator. the comparison signal is output from the sens1 and sens2 pins. (address d11 001101 d6 ) the comparison signal is as follows. sens1 pin balh sens2 pin ball h l h h l h v in < v l < v h v l < v in < v h v l < v h < v in v h : high level threshold value v in : window comparator input signal v l : low level threshold value sens1 pin tgh h h l sens2 pin tgl v h v l v in (1) (2) (3) the gain should be adjusted so that the sens1 and sens2 pins are as shown in status (2). when the teo signal level is low and tgh (sens1 pin) does not go low, the gain should be raised with the tgfl command for adjustment. if the adjustment does not bring the result of low, check the pulse duty of tgl (sens2 pin).
21 CXA2542AR apc & laser power control ld rftc rf_o rf_i pd v ee v cc r8 10k v ee r5 55k r10 56k r12 56k r11 10k r4 10k r6 1k ldon r14 12.5k v l vref lpc on/off 50%/30% 670mv r9 41k vc r7 13k v ee rf r13 1m v ee v ee c4 1 r1 22 c2 100 c1 1 v ee r3 100 r2 500 130mv gnd ld pd l1 10h v cc c3 0.01 30 31 33 34 35 0.684v for 4.5v or more 0.57v for 3.6v or less fok mirr apc when the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. the apc circuit is used to maintain the optical power output at a constant level. the laser diode current is controlled according to the monitor photodiode output. laser power control the rf level is stabilized by attaching an offset to the apc v l and controlling the laser power in sync with the rf level fluctuations. the rf_o and rf_i levels are compared and the larger of the two is smoothed by the rftc's external cr. this signal is then compared with the reference level. the laser power is controlled by attaching an offset to v l according to the results of comparison with the reference level. the reference level is set to 0.57v for the power supply of 3.6v or less and to 0.684v for 4.5v or more. lpc on/off and ld on/off control is performed with commands. the laser power control limit can also be switched between 50% and 17% with commands. lpc off on on 50% 30% approximately 1.27v approximately 1.27v 625mv approximately 1.27v 375mv lpcl v l variable range
22 CXA2542AR center voltage generation circuit (the figure below shows a single voltage application; connect to gnd for dual power supplies.) the maximum current is approximately 3ma. the output impedance is approximately 50 ? . 50 v cc v ee vc connected internally to the v ee pin. 30k 30k v cc gnd vc 46
23 CXA2542AR focus servo 6k 54k fe 2200p 10k feo fei 100k dfct fs4 focus phase compensation 68k 100k fe_o focus coil fe_m 100k iset 60k 11 22 fs2 fs1 50k 50k 4.7 0.015 510k 0.1 fset flb 40k 0.1 0.1 680k fdfct fgd srch sens selector fs3 10k 0.022 fzc 300k fzc sens1 charge up 47 48 1 2 3 4 10 7 16 6 5 23 the above figure shows a block diagram of the focus servo. ordinarily the fe signal is input to the focus phase compensation circuit through a 68k ? resistance; however, when dfct is detected, the fe signal is switched to pass through a low-pass filter formed by the internal 100k ? resistance and the capacitance connected to pin 2. when this dfct prevention circuit is not used, leave pin 2 open. the defect switch operation can be enabled and disabled with command. the capacitor connected between pin 4 and gnd is a time constant to boost the low frequency in the normal playback state. the peak frequency of the focus phase compensation is approximately 1.2khz when a resistance of 510k ? is connected to pin 10. the focus search level is approximately 1.1vp-p when using the constants indicated in the above figure. this level is inversely proportional to the resistance connected between pin 16 and v ee . however, changing this resistance also changes the level of the track jump and sled kick as well. the fzc comparator inverted input is set to 10% of vcc and vc (pin 46); (vcc vc) 10%. ? 510k ? resistance is recommended for pin 10.
24 CXA2542AR tracking and sled servo + te teo buffer amp lpfi 0.01 0.01 150k 100k dfct 100k tdfct 0.1 atsc 470p 330k 47k 0.047 0.022 tzc tzc tgu tg2 0.033 470k tg2 20k 510k 0.015 fset tracking phase compensation 10k 90k tm4 tm3 11a 11a 100k tracking coil 82k 15k 22 3.3 sl_p tm2 tm6 tm5 22a 22a 100k 1k 1k 100k atsc 8.2k 120k 0.015 m sled motor sl_o sl_m tm1 680k 680k 66p ta_m ta_o tg1 tm7 gain window comparator balance window comparator sens selector balh ball tgh tgl sens1 sens2 te 24 23 15 14 13 11 12 10 9 8 44 43 45 42 41 the above figure shows a block diagram of the tracking and sled servo. the capacitor connected between pins 8 and 9 is a time constant to cut the high-frequency gain when tg2 is off. the peak frequency of the tracking phase compensation is approximately 1.2khz when a 510k ? resistance is connected to pin 10. in the CXA2542AR, tg1 and tg2 are inter-linked switches. to jump tracks in fwd and rev directions, turn tm3 or tm4 on. during this time, the peak voltage applied to the tracking coil is determined by the tm3 or tm4 current and the feedback resistance from pin 11. to be more specific, track jump peak voltage = tm3 (or tm4) current feedback resistance value the fwd and rev sled kick is performed by turning tm5 or tm6 on. during this time, the peak voltage applied to the sled motor is determined by the tm5 or tm6 current and the feedback resistance from pin 14; sled kick peak voltage = tm5 (or tm6) current feedback resistance the values of the current for each switch are determined by the resistance connected between pin 16 and v ee . when this resistance is 60k ? : tm3 (or tm4) = 11a, and tm5 (or tm6) = 22a. as is the case with the fe signal, the te signal is switched to pass through a low-pass filter formed by the internal resistance (100k ? ) and the capacitance connected to pin 45.
the iset pin is used to connect external resistance. this external resistance sets the current which determines the focus search, track jump, and sled kick levels. focus search current i 1 = (v bg : approximately 1.27v) i 2 = 2i 1 track jump current (tm3 and tm4 current) i = sled kick current (tm5 and tm6 current, when d1 = d0 = 0 during 1x$ commands) i = use external resistance of between 30k ? and 240k ? . using external resistance outside this range may cause oscillation. 25 CXA2542AR fs1 i 2 i 1 v bg r 1 2 v bg r v bg r 1 2
26 CXA2542AR focus ok circuit rf 15k 56k vg 44k 20k v cc 0.63v rf_o rf_i fok 1 focus ok amp focus ok comparator c5 0.01 31 30 25 defect lpc mirr v4 the focus ok circuit creates the timing window okaying the focus servo from the focus search state. the hpf output is obtained at pin 30 from pin 31 (rf signal), and the lpf output (opposite phase) of the focus ok amplifier output is also obtained. v4 is set in v3=v4 to cancel v3 of the rf amplifier voltage v rfo. the focus ok output is inverted when v rfi v rfo 0.51v. note that, c5 determines the time constant of the hpf for the mirror circuit and the lpf of the focus ok amplifier. ordinarily, with a c5 equal to 0.01f selected, the fc is equal to 1khz, and block error rate degradation brought about by rf envelope defects caused by scratched discs can be prevented. defect circuit after differentiated with the capacitance coupling and then inverted, the rf_o signal is bottom held by means of the long and short time constants. the short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms. the long time-constant bottom hold keeps the mirror level prior to the defect and shifts the level. the long and short time-constant signals are compared to generate the mirror defect detection signal. be sure to disable dfct ($34x) during focus search because the focus drive waveform is muted. 43k 2 b defect amp cc1 cc2 sens1 cb 0.01 0.068 defect sw defect comparator defect bottom hold e c d 26 sens2 sens selector dfct1 flip flop dfct2 27 24 23 interruption comparator f 0.5v a rf fok 30 e d c b a bottom hold (1) solid line defect amp rfo sens1 bottom hold (2) broken line h l f int h l
27 CXA2542AR mirror circuit the mirror circuit performs peak and bottom hold after the rfi signal has been inverting amplified. for the peak hold, a time constant can follow a 30khz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. the dc restored-envelope signal j is obtained by amplifying the difference between the peak and bottom hold signals h and i. signal j has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal k. if the value of c5 is made smaller, the low frequency component of the rf signal is cut off and the amplification of the signal g gets small. then, that of the signal j gets also small and the signal k level becomes low, resulting in the short mirror output pulse width. accordingly, when on the disc track, the mirror output is low; when between tracks (mirrored portion), it is high; and when a defect is detected, it is high. the mirror hold time constant must be sufficiently large compared with the traverse signal. rf 0.033 rf_o rf_i cp mirror comparator peak & bottom hold 1.4 k mirror hold amp j h i 1 g mirror amp sens selector mirr sens2 31 30 29 24 fok defect fok lpc c5 0.01 1v 51k 22k 1.5k rf_o h l 0v 0v 0v 0v g (rf_i) h (peak hold) i (bottom hold) (mirror hold) j k mirr
28 CXA2542AR sens selector sens1 fzc dfct1 tzc balh tgh foh atsc sens2 high-z dfct2 mirr ball tgl fol 23 24 what is output to the sens1 and sens2 pins varies according to the address input to the data pin. data (pin 20) 8-bit transfer sens1 sens2 address d7 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 x x x x x x x x x x x x x x x x x x x x fzc dfct1 tzc h (high-z) h (high-z) dfct2 mirr h (high-z) d6 d5 d4 d3 d2 d1 d0 data data (pin 20) 12-bit transfer sens1 sens2 address d11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x balh tgh foh atsc ball tgl fol h (high-z) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data notes) 12-bit transfer should be performed during $3xx commands. when 8 bits are transferred, sens1 and sens2 are switched according to the d3 and d2 data. sens1 and sens2 are switched without latching.
29 CXA2542AR commands the input data to operate this ic is configured as 8-bit/12-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $xx, where x is a hexadecimal numeral between 0 and f/$xxx for 12-bit. commands for the CXA2542AR can be broadly divided into four groups ranging in value from $0x, $1x, $2x, $3xx. 1. $0x (fzc at sens1 pin (pin 23), h (hi-z) at sens2 pin (pin 24)) these commands are related to the focus servo control. the bit configuration is as shown below. d7 d6 d5 d4 d3 d2 d1 d0 0000fs4 fs2 fs1 four focus related switches exist: fs1, fs2, fs4 and dfct. $00 when fs1 = 0, pin 7 is charged to (22a 11a) 50k ? = 0.55v. if, in addition, fs2 = 0, this voltage is no longer transferred, and the output at pin 5 becomes 0v. $02 from the state described above, the only fs2 becomes 1. when this occurs, a negative signal is output to pin 5. this voltage level is obtained by equation 1 below. (22a 11a) 50k ? .... equation 1 the srch down speed can be increased by the charge up circuit. $03 from the state described above, fs1 becomes 1, and a current source of +22a is split off. then, a cr charge/discharge circuit is formed, and the voltage at pin 7 decreases with the time as shown in fig. 1 below. fig. 1. voltage at pin 7 when fs1 goes from 0 1 this time constant is obtained with the 50k ? resistance and an external capacitor. by alternating the commands between $02 and $03, the focus search voltage can be constructed. (fig. 2) fig. 2. constructing the search voltage by alternating between $02 and $03. (voltage at pin 5) resistance between pins 5 and 6 50k ? 0v 0v $0002 03 02 03 00 02
30 CXA2542AR the instant when the signal is brought into focus. $08 $03 ($00) $02 (20ms) (200ms) drive voltage focus error sens1 (fzc) focus ok ? the broken lines in the figure indicate the voltage assuming the signal not in focus. 1-1. fs4 this switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo on and off. $00 $08 focus off focus on 1-2. procedure of focus activation for description, suppose that the polarity is as described below. a) the lens is searching the disc from far to near; b) the output voltage (pin 5) is changing from negative to positive; and c) the focus s-curve is varying as shown below. fig. 3. s-curve the focus servo is activated at the operating point indicated by a in fig. 3. ordinarily, focus searching and turning the focus servo switch on are performed while the focus s-curve transits the point a indicated in fig. 3. to prevent misoperation, this signal is anded with the focus ok signal. in this ic, the fzc (focus zero cross) signal is output from the sens1 pin (pin 23) as the point a transit signal. in addition, focus ok is output as a signal indicating that the signal is in focus (can be in focus in this case). following the line of the above description, focusing can be well obtained by observing the following timing chart. t a fig. 4. focus on timing chart
31 CXA2542AR 2. $1x (dfct1 at sens1 pin (pin 23), dfct2 at sens2 pin (pin 24)) these commands deal with switching tg1/tg2, brake circuit on/off, and the sled kick output. the bit configuration is as follows: d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 tg1, tg2 brake sled kick circuit level on/off on/off tg1, tg2, tm7 the purpose of tg1 and tg2 is to switch the tracking servo gain up/normal. tg1 and tg2 are interlinked switches. the brake circuit (tm7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. for the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the rf envelope and the tracking error is 180 out-of-phase to cut the unneeded portion of the tracking error and apply braking. note that the time from the high to low transition of fzc to the time command $08 is asserted must be minimized. to do this, the software sequence shown in b is better than the sequence shown in a. fzc ? no yes f. ok? no transfer $08 latch fzc ? no f. ok? no transfer $08 latch (a) (b) yes yes yes fig. 5. poor and good software command sequences d1 (ps1) 0 0 1 1 d0 (ps0) 0 1 0 1 1 2 3 4 relative value sled kick level
32 CXA2542AR envelope detection waveform shaping waveform shaping edge detection [ ? b] [ ? e] rf_i tzc CXA2542AR (latch) q d ck (mirr) [ ? c] [ ? f] [ ? g] brk d2 tm7 low: open high: make [ ? a] [ ? d] [ ? h] 30 44 fig. 6. tm7 movement during braking operation from inner to outer track 0v from outer to inner track ("mirr") ("tzc") braking is applied from here. [ ? a] [ ? b] [ ? c] [ ? d] [ ? e] [ ? f] [ ? g] [ ? h] fig. 7. internal waveform 3. $2x (tzc at sens1 pin (pin 23), mirr at sens2 pin (pin 24)) these commands deal with turning the tracking servo and sled servo on/off, and creating the jump pulse and fast forward pulse during access operations. d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 tracking sled control control 00 off 00 off 01 servo on 01 servo on 10 f-jump 10 f-fast forward 11 r-jump 11 r-fast forward tm1, tm3, tm4, tm2, tm5, tm6
33 CXA2542AR 4. $3xx these commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. in the initial resetting state, bal1 to bal4 switches and tog1 to tog4 switches are on. also, the ifb1 to ifb6 switches are on. balance adjustment the balance adjustment switches bal1 to bal4 can be controlled by setting d6 = 0 and d7 = 0. the switches are set using d0 to d3. at this time, sens1 outputs balh and sens2 outputs ball. data is set by specifying switch conditions d0 to d3 and sending a latch pulse with d6 = 0 and d7 = 0. sending a latch pulse with d6, d7 0 does not change the balance switch settings. start c.out is the frequency high enough ? sens1/2 balance ok ? adjustment completed bal1 to bal4 switch control yes no gain adjustment the gain adjustment switches tog1 to tog4 can be controlled by setting d6 = 1 and d7 = 0. these switches are set using d0 to d3. at this time, sens1 outputs tgh and sens2 outputs tgl. in a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions d0 to d3 and sending a latch pulse with d6 = 1 and d7 = 0. start sens1/2 gain ok ? adjustment completed tog1 to tog4 switch control yes no balance adjustment gain adjustment
34 CXA2542AR focus bias adjustment the focus bias adjustment switches ifb1 to ifb6 can be controlled by setting d6 = 0 and d7 = 1. the switches are set using d0 to d5. at this time, sens1 outputs foh and sens2 outputs fol. data is set by specifying switch conditions d0 to d5 and sending a latch pulse with d6 = 0 and d7 = 1. start sens1/2 bias ok ? adjustment completed ifb1 to ifb6 switch control yes no focus bias adjustment method tgfl the tracking gain can be switched by setting d5 with d6 = 1 and d7 = 0. the tracking gain is gain up with d5 = 1 and normal gain with d5 = 0. the teo signal level can be made higher by approximately 6db for gain up. when the teo signal level is low and tgh (sens1 pin) does not go low during tracking adjustment, the gain should be raised with the tgfl command for adjustment. lpc the laser power control circuit can be turned on and off by setting d0 with d6 = 1 and d7 = 1. the circuit is on with d0 = 1 and off with d0 = 0. lpcl the laser power control limit can be switched between 30% and 50% by setting d1 with d6 = 1 and d7 = 1. the control limit is 30% with d1 = 0 and 50% with d1 = 1. ldon the laser diode can be turned on and off by setting d2 with d6 = 1 and d7 = 1. the laser diode is on with d2 = 1 and off with d2 = 0.
atsc the anti-shock function can be controlled by setting d3 with d6 = 1 and d7 = 1. this function is disabled with d3 = 1 and enabled with d3 = 0. at this time, sens1 outputs atsc. even if atsc is disabled, atsc is output to sens1. when an anti-shock signal is generated during the enable status, tg1 and tg2 switch to gain up mode. (in the block diagram, tg1 is set to the side and tg2 is off. even if tg1 and tg2 are in normal mode, they switch to gain up mode in conjunction with atsc.) when the anti-shock function is not used, pin 43 (atsc) should be connected to vc. rdfct2 dfct2 can be reset by setting d4 with d6 = 1 and d7 = 1. dfct2 is reset with d4 = 1. after a reset, high is held when dfct1 rises. during $1x commands, dfct2 is output from sens2. dfct2 operates even if dfct is disabled. whether or not dfct rises at the proper timing for the microcomputer can also be confirmed. int the interruption (scratched disc) countermeasure circuit can be set to the operating status by setting d5 with d6 = 1 and d7 = 1. this circuit is enabled when d5 = 1 and disabled when d5 = 0. even if dfct1 does not rise, this circuit is effective for scratched discs which cause mirr to rise. when mirr rises, the dfct switch is routed through the low-pass filter. the interruption countermeasure circuit is forcibly turned off regardless of the command when the tracking gain is increased. (including when the gain is increased by atsc) even if dfct is disabled, the interruption countermeasure circuit operates when int is enabled. 35 CXA2542AR
36 CXA2542AR cpu serial interface timing chart t wck d0 d1 d2 d3 d4 d5 d6 d7 d0 t wck t su 1/fck t h t cd t wl t d data clk xlt item clock frequency clock pulse width setup time hold time delay time latch pulse width data transfer interval low level input voltage high level input voltage symbol fck fwck t su t h t d t wl t cd v il v ih min. 500 500 500 500 1000 1000 0.0 (v cc v ee ) 0.9 typ. max. unit mhz ns ns ns ns ns ns v v 1 (v cc v ee ) 0.1 v cc (v cc = 3.0v)
37 CXA2542AR system control focus control tracking control tracking sled mode d7 d6 d5 d4 fs4 focus 1 = on 0 = off tg1, tg2 1 = gain up 0 = normal 0 0 0 0 0 0 0 0 1 0 1 0 brake 1 = enable 0 = disable fs2 srch on 1 = on 0 = off sled kick + 2 fs2 srch up 1 = up 0 = down sled kick + 1 fzc dfct1 tzc tracking mode ? 1 sled mode ? 2 address d3 d2 d1 d0 data data (pin 20) 8-bit transfer sens1 h (high-z) dfct2 mirr sens2 ? 1 tracking mode fwd jump rev jump d3 0 0 1 1 d2 0 1 0 1 off on ? 2 sled mode fwd move rev move d1 0 0 1 1 d0 0 1 0 1 off on item
38 CXA2542AR e-f balance tracking gain focus bias others d11 d10 d9 d8 dfct 1 = disable 0 = enable tgfl 1 = gain up 0 = normal ifb6 1 = off 0 = on int 1 = enable 0 = disable 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 d7 d6 ifb5 1 = off 0 = on rdfct2 1 = reset 0 = normal bal4 1 = off 0 = on tog4 1 = off 0 = on ifb4 1 = off 0 = on atsc 1 = disable 0 = enable bal3 1 = off 0 = on tog3 1 = off 0 = on ifb3 1 = off 0 = on ldon 1 = on 0 = off balh tgh foh atsc address d5 d4 d3 d2 bal2 1 = off 0 = on tog2 1 = off 0 = on ifb2 1 = off 0 = on lpcl 1 = 50% 0 = 30% bal1 1 = off 0 = on tog1 1 = off 0 = on ifb1 1 = off 0 = on lpc 1 = on 0 = off d1 d0 data data (pin 20) 12-bit transfer sens1 ball tgl fol h (high-z) sens2 item notes) when atsc is enabled, even if tg1 and tg2 are in normal mode, tg1 and tg2 switch to gain up mode in conjunction with atsc. int is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased b y atsc) when reset sens1 = fzc sens2 = high (hi-z) rdfct2 = 1 (reset) ifb1 to ifb6 = 0 (switch on) tog1 to tog4 = 0 (switch on) bal1 to bal4 = 1 (switch on) other data is "0".
39 CXA2542AR serial data truth table serial data focus control 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001 0001 1010 0001 1011 0001 1100 0001 1101 0001 1110 0001 1111 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex functions fs4 brak sld kick kick +1 kick +2 fig. 6 d2 tg1 tg2 tracking control fs2 fs1 notes) fs1 1: off 0: on fs2 1: on 0: off fs4 in the block diagram: 1: sw side 0: sw side notes) tg1 in the block diagram: 1: sw side 0: sw side tg2 1: off 0: on brake when d2 in fig. 6 is: 1: 1 0: 0 sled kick level d1 0 0 1 1 0 1 0 1 1 2 3 4 d0 relative value
40 CXA2542AR serial data tracking/sled mode 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 hex function tm6 tm5 tm4 tm3 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 tm2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 tm1 notes) tm1/tm2 in the block diagram: 1: sw side 0: sw side tm3/tm4/tm5/tm6 1: on 0: off
41 CXA2542AR serial data $3xx 0011 0000 0000 0011 0000 0001 0011 0000 0010 0011 0000 0011 0011 0000 0100 0011 0000 0101 0011 0000 0110 0011 0000 0111 0011 0000 1000 0011 0000 1001 0011 0000 1010 0011 0000 1011 0011 0000 1100 0011 0000 1101 0011 0000 1110 0011 0000 1111 0011 0001 0000 0011 0001 0001 0011 0001 0010 0011 0001 0011 0011 0001 0100 0011 0001 0101 0011 0001 0110 0011 0001 0111 0011 0001 1000 0011 0001 1001 0011 0001 1010 0011 0001 1011 0011 0001 1100 0011 0001 1101 0011 0001 1110 0011 0001 1111 0011 0010 0000 0011 0010 0001 0011 0010 0010 0011 0010 0011 0011 0010 0100 0011 0010 0101 0011 0010 0110 0011 0010 0111 0011 0010 1000 0011 0010 1001 0011 0010 1010 0011 0010 1011 0011 0010 1100 0011 0010 1101 0011 0010 1110 0011 0010 1111 $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30a $30b $30c $30d $30e $30f $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31a $31b $31c $31d $31e $31f $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32a $32b $32c $32d $32e $32f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e d d d d d d d d d d d d d d d d hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
42 CXA2542AR serial data $3xx 0011 0011 0000 0011 0011 0001 0011 0011 0010 0011 0011 0011 0011 0011 0100 0011 0011 0101 0011 0011 0110 0011 0011 0111 0011 0011 1000 0011 0011 1001 0011 0011 1010 0011 0011 1011 0011 0011 1100 0011 0011 1101 0011 0011 1110 0011 0011 1111 0011 0100 0000 0011 0100 0001 0011 0100 0010 0011 0100 0011 0011 0100 0100 0011 0100 0101 0011 0100 0110 0011 0100 0111 0011 0100 1000 0011 0100 1001 0011 0100 1010 0011 0100 1011 0011 0100 1100 0011 0100 1101 0011 0100 1110 0011 0100 1111 0011 0101 0000 0011 0101 0001 0011 0101 0010 0011 0101 0011 0011 0101 0100 0011 0101 0101 0011 0101 0110 0011 0101 0111 0011 0101 1000 0011 0101 1001 0011 0101 1010 0011 0101 1011 0011 0101 1100 0011 0101 1101 0011 0101 1110 0011 0101 1111 $330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33a $33b $33c $33d $33e $33f $340 $341 $342 $343 $344 $345 $346 $347 $348 $349 $34a $34b $34c $34d $34e $34f $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35a $35b $35c $35d $35e $35f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 d d d d d d d d d d d d d d d d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
43 CXA2542AR serial data $3xx 0011 0110 0000 0011 0110 0001 0011 0110 0010 0011 0110 0011 0011 0110 0100 0011 0110 0101 0011 0110 0110 0011 0110 0111 0011 0110 1000 0011 0110 1001 0011 0110 1010 0011 0110 1011 0011 0110 1100 0011 0110 1101 0011 0110 1110 0011 0110 1111 0011 0111 0000 0011 0111 0001 0011 0111 0010 0011 0111 0011 0011 0111 0100 0011 0111 0101 0011 0111 0110 0011 0111 0111 0011 0111 1000 0011 0111 1001 0011 0111 1010 0011 0111 1011 0011 0111 1100 0011 0111 1101 0011 0111 1110 0011 0111 1111 0011 1000 0000 0011 1000 0001 0011 1000 0010 0011 1000 0011 0011 1000 0100 0011 1000 0101 0011 1000 0110 0011 1000 0111 0011 1000 1000 0011 1000 1001 0011 1000 1010 0011 1000 1011 0011 1000 1100 0011 1000 1101 0011 1000 1110 0011 1000 1111 $360 $361 $362 $363 $364 $365 $366 $367 $368 $369 $36a $36b $36c $36d $36e $36f $370 $371 $372 $373 $374 $375 $376 $377 $378 $379 $37a $37b $37c $37d $37e $37f $380 $381 $382 $383 $384 $385 $386 $387 $388 $389 $38a $38b $38c $38d $38e $38f 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
44 CXA2542AR serial data $3xx 0011 1001 0000 0011 1001 0001 0011 1001 0010 0011 1001 0011 0011 1001 0100 0011 1001 0101 0011 1001 0110 0011 1001 0111 0011 1001 1000 0011 1001 1001 0011 1001 1010 0011 1001 1011 0011 1001 1100 0011 1001 1101 0011 1001 1110 0011 1001 1111 0011 1010 0000 0011 1010 0001 0011 1010 0010 0011 1010 0011 0011 1010 0100 0011 1010 0101 0011 1010 0110 0011 1010 0111 0011 1010 1000 0011 1010 1001 0011 1010 1010 0011 1010 1011 0011 1010 1100 0011 1010 1101 0011 1010 1110 0011 1010 1111 0011 1011 0000 0011 1011 0001 0011 1011 0010 0011 1011 0011 0011 1011 0100 0011 1011 0101 0011 1011 0110 0011 1011 0111 0011 1011 1000 0011 1011 1001 0011 1011 1010 0011 1011 1011 0011 1011 1100 0011 1011 1101 0011 1011 1110 0011 1011 1111 $390 $391 $392 $393 $394 $395 $396 $397 $398 $399 $39a $39b $39c $39d $39e $39f $3a0 $3a1 $3a2 $3a3 $3a4 $3a5 $3a6 $3a7 $3a8 $3a9 $3aa $3ab $3ac $3ad $3ae $3af $3b0 $3b1 $3b2 $3b3 $3b4 $3b5 $3b6 $3b7 $3b8 $3b9 $3ba $3bb $3bc $3bd $3be $3bf 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
45 CXA2542AR serial data $3xx 0011 1100 0000 0011 1100 0001 0011 1100 0010 0011 1100 0011 0011 1100 0100 0011 1100 0101 0011 1100 0110 0011 1100 0111 0011 1100 1000 0011 1100 1001 0011 1100 1010 0011 1100 1011 0011 1100 1100 0011 1100 1101 0011 1100 1110 0011 1100 1111 0011 1101 0000 0011 1101 0001 0011 1101 0010 0011 1101 0011 0011 1101 0100 0011 1101 0101 0011 1101 0110 0011 1101 0111 0011 1101 1000 0011 1101 1001 0011 1101 1010 0011 1101 1011 0011 1101 1100 0011 1101 1101 0011 1101 1110 0011 1101 1111 0011 1110 0000 0011 1110 0001 0011 1110 0010 0011 1110 0011 0011 1110 0100 0011 1110 0101 0011 1110 0110 0011 1110 0111 0011 1110 1000 0011 1110 1001 0011 1110 1010 0011 1110 1011 0011 1110 1100 0011 1110 1101 0011 1110 1110 0011 1110 1111 $3c0 $3c1 $3c2 $3c3 $3c4 $3c5 $3c6 $3c7 $3c8 $3c9 $3ca $3cb $3cc $3cd $3ce $3cf $3d0 $3d1 $3d2 $3d3 $3d4 $3d5 $3d6 $3d7 $3d8 $3d9 $3da $3db $3dc $3dd $3de $3df $3e0 $3e1 $3e2 $3e3 $3e4 $3e5 $3e6 $3e7 $3e8 $3e9 $3ea $3eb $3ec $3ed $3ee $3ef 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e e e e e e e e d d d d d d d d e e e e e e e e d d d d d d d d e e e e e e e e d d d d d d d d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
notes) 0 means off and 1 means on for tog sw and bal sw. these are not equal to the setting values of each bit for serial data. " " in the truth table indicates that the status does not change. tgfl in the block diagram: 1: sw side 0: sw side atsc e: enable/d: disable dfct e: enable/d: disable 46 CXA2542AR serial data $3xx 0011 1111 0000 0011 1111 0001 0011 1111 0010 0011 1111 0011 0011 1111 0100 0011 1111 0101 0011 1111 0110 0011 1111 0111 0011 1111 1000 0011 1111 1001 0011 1111 1010 0011 1111 1011 0011 1111 1100 0011 1111 1101 0011 1111 1110 0011 1111 1111 $3f0 $3f1 $3f2 $3f3 $3f4 $3f5 $3f6 $3f7 $3f8 $3f9 $3fa $3fb $3fc $3fd $3fe $3ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 e e e e e e e e d d d d d d d d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hex bal sw 43214321 4 5 6 321 tog sw ifb sw int rdf ct2 atsc ldon lpcl lpc dfct tgfl
47 CXA2542AR initial state (resetting state) item focus control tracking control tracking sled mode address d7 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 $00 $10 $20 d6 d5 d4 d3 d2 d1 d0 data hex item e-f balance tracking gain focus bias others address d11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 $300 $340 $380 $3d0 d10 d9 d8 d7 d6 d5 d4 0 0 0 0 d3 0 0 0 0 d2 0 0 0 0 d1 0 0 0 0 d0 data hex the above data means the following operation modes. focus control : focus off, focus search off, focus seach down tracking control : tg1-tg2 normal, brake disable, sled kick relative level value 1 tracking sled mode : tracking off, sled off e-f balance : bal1 to bal4 = 0 (switch on). dfct enable tracking gain : tog1 to tog4 = 0 (switch on), tgfl normal focus bias : ifb1 to ifb6 = 0 (switch on) others : int disable, dfct2 reset, atsc enable, ldon off, lpcl 30%, lpc off
48 CXA2542AR 2. sled amplifier the sled amplifier may oscillate when used by the buffer amplifier. use with a gain of approximately 20db. 3. focus/tracking internal phase compensation and reference design material notes on operation 1. focus ok circuit 1) refer to the "description of operation" for the time constant setting of the focus ok amplifier lpf and the mirror amplifier hpf. 2) the equivalent circuit for the output pin (fok) is shown in the diagram below. v cc 20k 40k 100k v ee v ee r l fok v cc 25 the fok and comparator output are as follows: output voltage high : v fokh near vcc output voltage low : v fokl vsat (npn) + v ee item sd measurement pin conditions typ. unit 1.2khz gain 1.2khz phase 1.2khz gain 1.2khz phase 2.7khz gain 2.7khz phase 08 08 25 25 25 13 25 13 6 c flb = 0.1f c fgd = 0.1f 21.5 63 13 125 26.5 130 db deg db deg db deg c tgu = 0.1f 13 fcs trk 4. laser poser control the rf level is stabilized by attaching an offset to the apc v l and controlling the laser power in sync with the rf level fluctuations. the laser life is shortened by increasing the laser power when the less light is reflected from the disc. it is recommended that the typical laser power value is set lower to maintain the laser life. take care of the laser maximum ratings when using the laser power control circuit.
49 CXA2542AR package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : solder (0.18) (0.127) 0.18 ?0.03 + 0.08 0.127 ?0.02 +0.05 sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 0.02 + 0.05 a 1.5 0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0 ? to 10 ? detail a 0.13 m 0.5 s s b detail b : solder (0.18) (0.127) 0.18 0.03 + 0.08 0.127 0.02 +0.05 lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.

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